In the last lesson, we introduced simulating digital circuits with Prolog. More complicated circuts can be made from thee basics units shown in that lesson. Let's build one and have Prolog "simulate" what truth table for it.
Here's a more complicated circuit that uses two inverters, two AND gates and an OR gate.
Note as the inputs and outputs we've labeled in this figure map into the same variables names
in the circuit(A,B,C,D) clause below. We've also put in the Prolog definitions for
or and and. Notice how the internal inputs and outputs like X, U, V, and W are folded into the circuit for Prolog to unify.
Running the goal will simulate all possible inputs and outputs of the circuit.
Now you try. Run the goal and see how Prolog exhaustively simulates the circuit.
Type your code here:
See your results here:
You can also insist on some value for a variable or variables. For example, running the goal
goal: circuit(A,B,C,1)., to insist that the output be a 1.
*This circuit was adapted from https://www.cs.hmc.edu/~keller/courses/cs60/slides/18.28.html
Share your code
Show a friend, family member, or teacher what you've done!